Intel CPU Leaky bucket

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Future 发表于 2018-9-7 15:08:24 | 显示全部楼层 |阅读模式
本帖最后由 Future 于 2018-9-7 15:16 编辑

Leaky bucket is implemented using a programmable free-runningcounter and a simple
threshold mechanism. Once the counter reaches the threshold value, aLEAK_STROBE
is generated which is used to decrement the rank level counter. Ifthe counter is already
at zero then strobe is ignored for that particular rank.

For example using a simple algorithm: if a system can tolerate 10errors in 24 hour
interval without taking any action, then the leaky bucket dripinterval can be
programmed to roughly 24 hour. So, if 10 errors occur within 24 hrs,leaky bucket will
deplete it and the rank level threshold will not cross the limit of10 errors. And even if
one additional error occurs within the 24 hrs then threshold will bereached and an
action needs to be taken.

There are 4 registerts about leaky bucket function, they are
leaky_bucket_cfg,
leaky_bucket_cntr_lo,
leaky_bucket_cntr_hi,
leaky_bkt_2nd_cntr_reg

Every memory rank has a group of these registers, let's introduceleaky_bucket_cfg register firstly,

1.jpg

From the above picture, we know that leaky_bucket_cfg register is the bit select mask of the two hot encodingthreshold,
leaky_bkt_cfg_hi is thehigher position of the mask, and leaky_bkt_cfg_lo is the lower position of themask.

When both counter bits selected by the LEAKY_BKT_CFG_HI andLEAKY_BKT_CFG_LO
are set, the 53b leaky bucket counter will be reset and the logicwill generate a LEAK
pulse to decrement the correctable error counter by 1.
MRC BIOS must program this register to any non-zero value beforeswitching to
NORMAL mode.

2nd, leaky_bucket_cntr_lo

3.jpg

This is the lower half of theleaky bucket counter. The full
counter is actually a 53b "DCLK" counter. There is a leastsignificant 11b of the 53b
counter is not captured in CSR. The carry "strobe" fromthe not-shown least significant
11b counter will trigger this 42b counter pair to count. The 42bcounter-pair is
compared with the two-hot encoding threshold specified by theLEAKY_BUCKET_CFG_HI
and LEAKY_BUCKET_CFG_LO pair. When the counter bits specified by the
LEAKY_BUCKET_CFG_HI and LEAKY_BUCKET_CFG_LO are both set, the 53bcounter is
reset and the leaky bucket logic will generate a LEAK strobe lastfor 1 DCLK.



3rd,leaky_bucket_cntr_hi

2.jpg

This is the upper half of theleaky bucket counter. The full
counter is actually a 53b "DCLK" counter. There is a leastsignificant 11b of the 53b
counter is not captured in CSR. The carry "strobe" fromthe not-shown least significant
11b counter will trigger this 42b counter pair to count. The 42bcounter-pair is
compared with the two-hot encoding threshold specified by theLEAKY_BUCKET_CFG_HI
and LEAKY_BUCKET_CFG_LO pair. When the counter bits specified by the
LEAKY_BUCKET_CFG_HI and LEAKY_BUCKET_CFG_LO are both set, the 53bcounter is
reset and the leaky bucket logic will generate a LEAK strobe lastfor 1 DCLK.



Below is an example :

      leaky_bkt_cfg_hi =18(0x12)
      leaky_bkt_cfg_lo =17(0x11)

So the leaky_bkt_cntr_lo bit 18, i.e. bit 29  of the full 53b counter is set to 1, theleaky_bkt_cntr_lo bit 17, i.e. bit 28  ofthe full 53b counter is set to 1,
If we combine the two bits , the full 53b counter is  110000000000000000000000000000b(0x30000000),the counter register leaky_bucket_cntr_lo and leaky_bucket_cntr_hi must reach0x30000000 DCLK, then  the leaky bucketlogic will generate a LEAK strobe last for 1 DCLK.


4th  leaky_bkt_2nd_cntr_reg

4.jpg

Secondary Leaky BucketCounter Limit (2b per DIMM).
This register defines secondary leaky bucket counter limit for all 8logical ranks within
channel. The counter logic will generate the secondary LEAK pulse todecrement the
rank's correctable error counter by 1 when the corresponding rankleaky bucket rank
counter roll over at the predefined counter limit. The counterincrement at the primary
leak pulse from the LEAKY_BUCKET_CNTR_LO and LEAKY_BUCKET_CNTR_HIlogic.


For example, if we set Bit[27:26]: Rank 5 Secondary Leaky BucketCounter Limit to 2, then ,
when bit 11:10: rank 5 secondary leaky bucket counter reach 2,
The counter logic will generate the secondary LEAK pulse todecrement the
rank's correctable error counter by 1, after that,  bit 11:10 roll back, and count again.

Following is part of intel leay bucket registers setting table forreference :

5.jpg









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xiaoming141 发表于 2018-9-11 19:21:44 | 显示全部楼层
Intel这套ECC的漏斗,用处蛮大的。AMD好像没有,要软件实现。。。
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